1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor substrate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of metal-oxide-semiconductor (xe2x80x9cMOSxe2x80x9d) transistors, source and drain regions may be doped to an opposite conductivity type (either n-type or p-type) than the substrate. N-type source/drain regions may be used to form n-channel transistors and p-type source/drain regions may be used to form p-channel transistors. In complementary MOS (xe2x80x9cCMOSxe2x80x9d) circuits, however, both n-channel and p-channel transistors are formed within the same substrate. Consequently, wells may be formed by selectively doping the region of the substrate underlying the subsequently formed gate conductors to allow a substrate of either conductivity type to be used. In general, wells may be doped to an opposite conductivity type than that of the source and drain regions. In this manner, n-channel transistors may be formed in p-type wells, while p-channel transistors may be formed in n-type wells. In some cases, additional dopants may be introduced into the substrate to form channel dopant regions within the wells. Preferably, the channel dopant regions may be the same conductivity type as the wells in which they reside. In general, channel dopant regions may be used to prevent punch-through and short channel effects of subsequently formed transistors.
In addition, the fabrication of MOS transistors typically includes the formation of isolation structures between the active areas of the device. In general, the isolation structures may define the field regions of the semiconductor substrate, while the area including the well regions and channel dopant regions may define the active areas of the substrate. One isolation technology used in the fabrication of integrated circuits involves local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d). In LOCOS processes, an oxide layer may be grown upon a silicon substrate and a silicon nitride (xe2x80x9cnitridexe2x80x9d) layer may be arranged upon the oxide layer. The surfaces of the field regions upon the silicon substrate may then be exposed by etching portions of the nitride layer and the oxide layer. Remaining portions of the nitride layer and oxide layer may cover active regions of the silicon substrate, thereby serving as a mask to prevent oxidation of these regions in subsequent steps. An implant may then be performed in the field region to create a channel-stop doping layer and the exposed portion of the silicon substrate within the field region may be oxidized. By growing a thick oxide film within isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing may help prevent the establishment of parasitic channels in the field regions.
Although LOCOS has remained a popular isolation technology, the LOCOS process described above has several problems. When growing the field oxide, oxide growth should ideally be contained within the field region. In reality, however, some oxide growth may occur in a lateral direction, causing the field oxide to grow under and lift the edges of the nitride layer. Because the shape of the field oxide at the nitride edges is that of a slowly tapering wedge that merges into the pad oxide, the wedge is often described as a bird""s beak. In many instances, formation of the bird""s beak can cause unacceptable encroachment of the field oxide into the active regions. In addition, the high temperatures associated with field oxide growth often cause the pre-implanted channel-stop dopant to migrate towards adjacent active regions. An increase in the dopant concentration near the edges of the field oxide can create a reduction in the drain current, an outcome that is often described as the narrow-width effect. Furthermore, thermal oxide growth is significantly less in small field regions (i.e., field areas of narrow lateral dimension) than in large field regions. Because of this reduction in oxide growth, an undesirable phenomenon known as the field-oxide-thinning effect may occur in small field regions. Field-oxide-thinning can produce problems with respect to field threshold voltage magnitudes, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Despite advances made to decrease the bird""s beak, channel-stop encroachment and non-planarity problems, it appears that LOCOS technology is still inadequate for sub-micron technologies. Many of the problems associated with LOCOS technology may be alleviated by an isolation technique known as trench isolation. A trench isolation fabrication process typically includes an initial step in which a trench is etched within a silicon substrate. The trench may then be filled with a dielectric, such as silicon dioxide. Some trench isolation processes also include an intermediate step of growing oxide on the trench floor and sidewalls before filling the trench with the dielectric. After the trench is filled, the upper surface of the dielectric may then be made coplanar with the upper surface of the silicon substrate to complete the fabrication of the isolation structure. The trench isolation process eliminates many of the problems of LOCOS techniques, including bird""s beak and channel-stop dopant redistribution. Trench isolation processes are also better suited than LOCOS processes for isolating densely spaced active devices having field regions less than one micron wide. In addition, trench isolation structures formed by trench isolation processes may be fully recessed, offering at least the potential for a planar surface. Moreover, field-oxide thinning in narrow isolation spaces is less likely to occur when using a trench isolation process.
Despite their many advantages over LOCOS techniques, trench isolation processes nevertheless have their own set of drawbacks. In particular, the threshold voltage magnitude, VT, of a transistor separated by trench isolation structures may decrease as the width of the transistor decreases. Such a phenomenon is sometimes referred to as the inverse narrow width effect (xe2x80x9cINWExe2x80x9d). In contrast, the threshold voltage magnitude of transistors separated by isolation regions fabricated from techniques other than trench isolation processes may increase as the width of the transistor decreases. It is postulated that the INWE may be related to fields generated by transistors and concentrated at sharp corners between the silicon substrate and trench isolation structures. In addition or alternatively, the INWE may be influenced by the diffusion of dopant atoms from the silicon into the isolation structures, thereby reducing the dopant concentration of the channel dopant regions of the transistors. In other cases, the isolation regions may extend below the active region of the silicon, forming a channel along the side of the active region. Each of these conditions, either independently or in combination, may result in a decrease of the threshold voltage magnitude of a subsequently formed transistor.
A threshold voltage magnitude lower than its design value is undesirable because leakage current is typically increased as threshold voltage magnitude is decreased. Conversely, high threshold voltage magnitudes may have an undesirable effect on performance of the circuit, particularly at low supply voltages. Therefore, it may be beneficial to maintain transistor threshold voltage magnitudes within predetermined ranges. Consequently, as transistor widths continue to decrease and the use of trench isolation techniques becomes more prevalent, methods for adjusting the threshold voltage magnitude of transistors will become increasingly necessary. One method of adjusting the threshold voltage magnitude of a transistor is to implant a greater concentration of impurities into the channel dopant region of a subsequently formed transistor. However, the INWE is dependent on the width of the transistor and therefore, relatively wide transistors may not be affected by the NWE as much as the narrow-width transistors. Implanting an increased concentration of impurities into channel dopant regions of subsequently formed relatively wide transistors may lead to an unnecessarily large threshold voltage magnitude for those transistors, which may degrade their performance. Therefore, the implantation of a greater concentration of impurities into channel dopant regions may be appropriate only for the narrow-width transistors.
As a result, the implantation of additional impurities may be cumbersome, time-consuming, and costly when transistors of different conductivity types and sizes are fabricated into the same integrated circuit. For example, narrow-width CMOS transistors (i.e. transistors with a width of less than approximately 1 micron) are sometimes fabricated along with relatively wide CMOS transistors (i.e. transistors with a width of greater than approximately 1 micron) within the same integrated circuit. A fabrication process for such a device may require at least four masking layers in order to form channel dopant regions with the appropriate impurity concentrations such that transistors with the appropriate threshold voltage magnitudes may be subsequently formed. For instance, the fabrication process may require a different masking layer for the formation of each channel dopant region (e.g., narrow NMOS, wide NMOS, narrow PMOS, and wide PMOS channel dopant regions). Alternatively, the fabrication process may include forming the PMOS transistor channel dopant regions with one masking layer and the NMOS transistor channel dopant regions with another masking layer, and then using two separate masking layers to implant additional impurities to increase or decrease the threshold voltage magnitudes of the subsequently formed transistors.
Accordingly, it would be advantageous to develop a method for forming a CMOS integrated circuit with differing transistor widths and conductivity types and comparable threshold voltage magnitudes. In particular, it would advantageous to form such an integrated circuit using fewer masking layers than conventional methods.
The problems outlined above may be in large part addressed by a method for processing a semiconductor substrate. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to threshold voltage magnitude above a desired value for a first transistor. Such a method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of a second transistor. In some embodiments, the method may include introducing compensation dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously. In such an embodiment, a net concentration of electrically active impurities within the first transistor channel dopant region may be greater than a net concentration of electrically active impurities within the second transistor channel dopant region prior to introducing the compensation dopants.
Consequently, an integrated circuit is provided which includes a first transistor formed upon a first channel dopant region having implanted impurities of both conductivity types. In particular, the first channel dopant region may include a greater concentration of implanted impurities of one conductivity type than a concentration of implanted impurities of the other conductivity type. In addition, the integrated circuit may include a second transistor formed upon a second channel dopant region having implanted impurities of the other conductivity type. In some embodiments, the width of the second transistor may be smaller than a width of the first transistor.
In an embodiment, the method described herein may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for a first transistor. Such a first implantation may include introducing dopants of a first conductivity type into exposed portions of the semiconductor substrate to form a channel dopant region for the first transistor. As such, the first transistor may be subsequently fabricated within a portion of the substrate receiving the first implantation. In addition, the method may include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of a second transistor. The second implantation may include introducing dopants of a second conductivity type into the channel dopant regions of the first and second transistors. In particular, the second implantation may include implanting a large enough concentration of impurities to counteract an inverse narrow width effect on the threshold voltage magnitude of the second transistor.
The method may further include performing a third implantation prior to the second implantation corresponding to a threshold voltage magnitude below a desired value of the second transistor. In particular, the third implantation may be conducted before or after the first implantation. Such a third implantation may include introducing dopants of the second conductivity type into exposed portions of the semiconductor substrate to form a channel dopant region for the second transistor. As such, the second transistor may be subsequently fabricated within a portion of the substrate receiving the third implantation. In a preferred embodiment, the second conductivity type is opposite of the first conductivity type. Moreover, a dose of the dopants of the first conductivity type may be approximately 0.5 times smaller to approximately 2.0 times larger than a dose of the dopants of the second conductivity type during the third implantation. Larger and smaller dose variations may be appropriate, however, depending on the design specifications of the device. In some embodiments, a width of the second transistor may be smaller than a width of the first transistor.
More generally, the method may include interchanging the first, second, and third implantations such that a threshold voltage magnitude of a first transistor subsequently formed within the substrate may be decreased while the threshold voltage magnitude of a second transistor subsequently formed within the substrate may be increased. In this manner, the reference of the 1st, 2nd, and 3rd implantations may not indicate the order in which the implantations are performed but rather distinguish the functions of implantations from each another. For example, the second implantation may be introduced prior to either of the first and third implantations. In such an embodiment, the second implantation may include introducing dopants into exposed portions of the substrate to form channel dopant regions for the first and second transistor. The introduction of the first and third implantations, in such an embodiment, may be interchanged such that they are conducted before or after one another. In an embodiment in which the first implantation includes the opposite conductivity type as the second implantation, the first implantation may include changing the net conductivity type of one of the channel dopant regions created by the second implantation. In an embodiment in which the third implantation includes the same conductivity type as the second implantation, the third implantation may be introduced into another of the channel dopant regions created by the second implantation to raise the threshold voltage of the transistor subsequently formed within the channel dopant region. In addition, the first and third implantations may include forming additional channel dopant regions of their respective conductivity type.
In an alternative embodiment, the second implantation may be introduced between the first and third implantations. In this manner, the sequence of implantations may include the first implantation followed by the second and third implantations, respectively. In such an embodiment, the second implantation may include lowering the threshold voltage magnitude of a first transistor subsequently formed within the channel dopant region formed by the first implantation. In addition, the second implantation may include introducing dopants into exposed portions of the substrate to form a channel dopant region for the second transistor. The third implantation may follow to increase the threshold voltage magnitude of the second transistor and form an additional channel dopant region of its respective conductivity type. Alternatively, the sequence of implantations may include the third implantation followed by the second and first implantations, respectively. In this manner, the second implantation may include raising the threshold voltage magnitude of a second transistor subsequently formed within the channel dopant region formed by the third implantation. In addition, the second implantation may include introducing dopants into exposed portions of the substrate to form channel dopant regions for the first transistor. The first implantation may follow to change the conductivity type of the channel dopant region formed by the second implantation for the first transistor. In addition, the first implantation may form another channel dopant region of its respective conductivity type.
In an embodiment, the method described herein may include decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In such an embodiment, decreasing the threshold voltage magnitude may include decreasing a net concentration of electrically active impurities of a first conductivity type within a channel dopant region of the first transistor. Increasing the threshold voltage magnitude, on the other hand, may include increasing the concentration of impurities of a second conductivity type within a channel dopant region of the second transistor. In some embodiments, increasing the concentration of impurities of the second conductivity type may include increasing the concentration of impurities by an amount between approximately 20% and approximately 100%. In addition or alternatively, increasing the threshold voltage magnitude of the second transistor may include increasing the threshold voltage magnitude by an amount between approximately 25 mV and approximately 300 mV.
In some embodiments, the second transistor may be a memory cell transistor, while the first transistor may be a non-memory cell transistor. In addition or alternatively, a width of the first transistor may be larger than a width of the second transistor. More specifically, the width of the first transistor may be at least approximately 2 times larger than the width of the second transistor. In some embodiments, the width of the first transistor may be at least approximately 100 times larger than the width of the second transistor. Alternatively, the width of the first transistor may be approximately the same width as the second transistor in some embodiments.
As stated above, a method for processing a semiconductor substrate is provided. Such a method may include introducing compensation dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region, simultaneously. In some embodiments, a net concentration of electrically active impurities within the first transistor channel dopant region may be greater than a net concentration of electrically active impurities within the second transistor channel dopant region prior to introducing the compensation dopants. Alternatively, the net concentration of electrically active impurities within the first transistor channel dopant region may be equal to or less than a net concentration of electrically active impurities within the second transistor channel dopant region prior to introducing the compensation dopants. In addition, the impurities of the first transistor channel dopant region prior to the introduction of the compensation dopants may include a net conductivity type opposite to that of the compensation dopants. On the contrary, the impurities of the second transistor channel dopant region prior to the introduction of the compensation dopants may include the same net conductivity type as the compensation dopants.
The method may further include introducing first channel dopants of the first conductivity type into the semiconductor substrate to form the first transistor channel dopant region. Such an implantation of first channel dopants may further form a third transistor channel dopant region of the same conductivity type as the first transistor channel dopant region. In addition, the method may include introducing second channel dopants of a second conductivity type into the semiconductor substrate to form the second transistor channel dopant region. Such an implantation of second channel dopants may further form a fourth transistor channel dopant region of the same conductivity type as the second transistor channel dopant region. Preferably, the second conductivity type is opposite to that of the first conductivity type. Moreover, introducing the first and second channel dopants may include implanting. In such an embodiment, a dose of the first channel dopants may be larger than a dose of the second channel dopants. Alternatively, the dose of the first channel dopants may be smaller than the dose of the second channel dopants.
The method may further include forming a patterned layer over the second transistor channel dopant region and the fourth transistor channel dopant region prior to introducing the first channel dopants. In addition or alternatively, the method may include forming a patterned layer over the first transistor channel dopant region and the third transistor channel dopant region prior to introducing the second channel dopants. In some embodiments, the method may include forming a patterned layer over the third transistor channel dopant region and the fourth transistor channel dopant region prior to introducing the compensation dopants. Introducing the compensation dopants may include increasing the threshold voltage magnitude of a subsequently formed transistor arranged above the second transistor channel dopant region by an amount between approximately 25 mV and approximately 300 mV. In addition or alternatively, introducing the compensation dopants may include decreasing the threshold voltage magnitude of a subsequently formed transistor arranged above the first transistor channel dopant region. In either embodiment, introducing the compensation dopants may include increasing the concentration of the second transistor channel dopant region by an amount between approximately 20% and approximately 100%.
In an embodiment, the method as described herein may be used to form an integrated circuit. Such an integrated circuit may include a first transistor with a first channel dopant region having implanted impurities of both conductivity types. More specifically, the first channel dopant region may include a greater concentration of implanted impurities of one conductivity type than a concentration of implanted impurities of the other conductivity type. In addition, the integrated circuit may include a second transistor with a second channel dopant region having implanted impurities of the same conductivity type as the impurities having the lesser concentration within the first channel dopant region. In some embodiments, a width of the second transistor may be smaller than a width of the first transistor.
Furthermore, the integrated circuit may include a third transistor with a third channel dopant region having implanted impurities of the same conductivity type as the impurities having the greater concentration within the first channel dopant region. In some cases, a width of the third transistor may be smaller than the width of the first transistor. Furthermore, the first and third transistors may include non-memory transistors. Moreover, the integrated circuit may further include a fourth transistor with a fourth channel dopant region having implanted impurities of the same conductivity type as the impurities having the lesser concentration within the first channel dopant region. In some cases, a width of the fourth transistor may be larger than the width of the second transistor. In some embodiments, the second and fourth transistors may include memory cell transistors.
The method described herein may offer several benefits. In particular, transistors of differing widths and conductivity types and comparable threshold voltage magnitudes may be formed within the same integrated circuit. For example, CMOS transistors of a narrow width may be formed along with CMOS transistors with a relatively larger width and have substantially the same threshold voltage magnitude. Moreover, narrow-width CMOS transistors may be formed to a desired threshold voltage magnitude without undesirably increasing the threshold voltage magnitude of the relatively larger-width CMOS transistors. Furthermore, channel dopant regions of such transistors may be formed in three or fewer masking layers. This is distinctly different from conventional methods for forming an integrated circuit with transistors of comparable threshold voltage magnitudes and differing widths and conductivity types. Such methods generally require four or more masking layers to fabricate such an integrated circuit. The reduction in the number of masking layers required may reduce fabrication costs and processing time, thereby increasing production throughput. In addition, the inverse narrow width effect of transistors formed between trench isolation structures may be counteracted with the method as described herein.